In recent years, there has been a growing number of references on radio frequency (RF) CMOS processes and the corresponding RF models for these technologies. This article aims to clarify what these RF CMOS processes truly mean and why they are crucial for RF circuit designers.
RF CMOS design can be examined from three main perspectives: first, low-frequency analog designers are transitioning their designs to higher frequencies; second, discrete RF/microwave engineers are shifting toward integrated solutions; and third, digital designers are pushing high-speed circuits like SERDES to the highest frequencies supported by the process. In all these scenarios, RF CMOS plays a vital role, and we will explore how the modeling of RF CMOS differs from traditional approaches.
**Substrate**
In traditional digital CMOS applications, the substrate is typically made of low-resistivity bulk silicon with a thin, high-resistivity epitaxial layer. This setup is optimized for latch-up performance and yield. However, when it comes to RF design, this standard approach presents several challenges.
The uniform thickness of metal interconnect layers in digital designs allows for consistent routing across all layers. While this is ideal for digital designers, it poses issues for RF engineers. The low-resistivity substrate leads to significant parasitic capacitance, which negatively affects the performance of RF components like inductors. Additionally, the tight coupling between the coil and the grounded substrate reduces inductance and Q-factor. Currents flowing through the substrate can travel long distances, causing unwanted interference. Moreover, adding more metal layers to increase Q has limited effectiveness due to their proximity to the shorted substrate.
So, what makes an RF CMOS process different? In many cases, it involves using a high-resistivity epitaxial layer throughout the substrate. This creates a second, smaller capacitor in series with the existing parasitic capacitances, effectively increasing the substrate impedance. As a result, parasitic capacitances behave differently at higher frequencies, allowing for better control over device performance. The increased Q of inductors is also attributed to the reduced current flow through the substrate, leading to improved isolation and performance.
Using thicker top metal layers or even copper instead of aluminum can further enhance the Q of coils. Despite these differences, RF CMOS devices still share many characteristics with standard digital processes, as the topmost layers maintain similar resistivity levels.
**BSIM3 Model**
The BSIM3 model is widely used in CMOS design, with various versions such as BSIM3v2 available. Its success stems from its ability to combine physical and empirical parameters, making it adaptable to new fabrication processes. Physical analysis helps predict behavior at smaller scales, while empirical data accounts for non-uniformities in real devices.
For RF designers, understanding how the BSIM3 model behaves at higher frequencies is essential. Foundries typically generate these models by fabricating devices with varying dimensions and measuring their DC characteristics to determine transconductance and impedance. Low-frequency capacitance measurements then fill in the capacitive parameters. Optimization tools like Hspice OpTImizer are used to refine the model for accurate predictions.
When discrepancies arise, modelers may create multiple parameter sets for different device sizes, ensuring accuracy across a wide range of scales. This approach results in a compact model that works efficiently with simulators and offers flexibility in layout design.
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